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PI2EQX3201BL
3.0Gbps 2 Differential Channel SATA i/m ReDriverTM with Equalization, De-emphasis and OOB
Features
* * * * * * * * * * SATA2 i/m, extended SATA2 Two Pairs of 3.0Gbps differential signal Adjustable Transmitter Emphasis & Amplitude Adjustable Receiver Equalization 100-Ohm Differential CML I/O's Input signal level detect and squelch for each channel Low Power (100mW per Channel) Stand-by Mode - Power Down State VDD Operating Range: 1.5V to 1.8V Packaging (Pb-free & Green): -- 36-pad TQFN (ZF36)
Description
Pericom Semiconductor's PI2EQX3201BL is a low power, signal ReDriver. The device provides programmable equalization, amplification, and de-emphasis by using 4 select bits, SEL[0:3], to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference. PI2EQX3201BL supports two 100-Ohm Differential CML data I/O's between the Protocol ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user's platform. The integrated equalization circuitry provides flexibility with signal integrity of the signal before the re-driver. Whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the signal after the re-driver. A low-level input signal detection and output squelch function is provided for each channel. Each channel operates fully independantly. When a channel is enabled (EN_x=1) and operating, that channels input signal level (on xI+/-) determines whether the output is enabled. If the input level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to providing signal re-conditioning, Pericom's PI2EQX3201BL also provides power management Stand-by mode operated by a Bus Enable pin.
Pin Description (Top-Side View)
SEL0_A SEL1_A SEL2_A SD_A SD_B SEL3_A
Block Diagram
Signal Detection
VDD
1 2 3 4 5 6 7 8 9 10 11 12 36 35
34
33
32
31
30
EN_B
29 28 27 26 25
EN_A
VDD A0+ A0GND GND VDD BI+ BIGND NC
CML xl + Equalizer xlSEL[0:1]_X SEL2_x SEL3_x Limiting Amp
xO-
AI
+
CML
AI
xO+
-
GND VDD VDD B0+ B0GND
GND
24 23 22 21 20 19
EN_X
Power Management
VDD
13
14
15
16
17
18
NC
SEL0_B
SEL1_B
SEL2_B
SEL3_B
NC
NC
Repeated 2 Times 08-0329
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NC
PS9003A
12/11/08
www..com
PI2EQX3201BL 3.0Gbps 2 Differential Channel Serial ReDriver Equalization, De-emphasis and Squelch
Pin Description
Pin # 2 3 27 26 22 21 7 8 30 29 4, 9, 20, 24, 25, Center Pad 11, 12, 17, 18, 19 36 35 34 33 13 14 32 15 31 16 1, 5, 6, 10, 23, 28 Pin Name AI+ AIAO+ AOBI+ BIBO+ BOEN_A EN_B GND NC SD_A SD_B SEL0_A SEL1_A SEL0_B SEL1_B SEL2_A SEL2_B SEL3_A SEL3_B VDD I/O I O I O I PWR O I I I I I I PWR Description CML Input Channel A with internal 50-Ohm pull down CML Output Channel A internal 50-Ohm pull up. Drives to output common mode voltage when input is Output Swing Control
SEL2_[A:B] 0 1 Swing 1x 1.2x
Output De-emphasis Adjustment
SEL3_[A:B] 0 1 De-emphasis 0dB -3.5dB
Equalizer Selection
SEL0_[A:B] 0 0 1 1 SEL1_[A:B] 0 1 0 1 Compliance Channel @ 1.5GHz no equalization 1.5dB 1.0dB 3.5dB 1.0dB 5.5dB 1.0dB
08-0329
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PS9003A
12/11/08
www..com
PI2EQX3201BL 3.0Gbps 2 Differential Channel Serial ReDriver Equalization, De-emphasis and Squelch
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature........................................................ -65C to +150C Supply Voltage to Ground Potential ................................... -0.5V to +2.5V DC SIG Voltage ..........................................................-0.5V to VDD +0.5V Current Output ................................................................-25mA to +25mA Power Dissipation Continous ......................................................... 500mW Operating Temperature ........................................................... -40 to +85C
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
AC/DC Electrical Characteristics (VDD = 1.4 to 1.9V)
Symbol IDD Pstandby Pactive18 Pidle18 Pactive15 Pidle15 tpd Parameter Power Supply Current Power, standby Power, active @ 1.8V Power, idle @ 1.8V Power, active @ 1.5V Power, idle @ 1.5V Latency Conditions EN_[A:B] = 0 VDD=1.8V, EN_[A:B] = 1, Vrx-diff-p Vth-sd VDD=1.8V, EN_[A:B] = 1, Vrx-diff-p < Vth-sd VDD=1.5V, EN_[A:B] = 1, Vrx-diff-p Vth-sd VDD=1.5V, EN_[A:B] = 1, Vrx-diff-p < Vth-sd From differential input to differential output Min. Typ. Max. 90 1 160 130 Units mA mW mW mW mW mW ns
125 100 100 80 2.0
CML Receiver Input Return Loss RLRX Differential Input Peak-toVRX-DIFFP-P peak Voltage AC Peak Common Mode VRX-CM-ACP Input Voltage VTH-SD ZRX-DIFF-DC ZRX-DC Equalization JRS JRM Residual Jitter(1,2) Random Jitter(1,2) Signal Detect Threshold DC Differential Input Impedance DC Input Impedance
50 MHz to 1.25 GHz 0.200
12
dB V 150 mV
EN_X = High
50 80 40 100 50
200 120 60 Ohm
Total Jitter Deterministic jitter 1.5
0.3 0.2
Ulp-p psrms
Notes 1. K28.7 pattern is applied differentially at point A as shown in Figure 1. 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 x RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. JItter is measured at 0V at point C of Figure 1.
08-0329
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www..com
PI2EQX3201BL 3.0Gbps 2 Differential Channel Serial ReDriver Equalization, De-emphasis and Squelch
FR4
Signal Source A B D.U.T. SmA Connector 30IN SmA Connector C
In
Out
Figure 1. Test Condition Referenced in the Electrical Characteristic Table
AC/DC Electrical Characteristics (VDD = 1.4V to 1.9V)
Symbol Parameter Differential Peak-to-peak Ouput Voltage SEL2_x = 0 VTX-DIFFP-P = 2 * |VTX-D+ - VTX-D-| SEL2_x = 1 Common-Mode Voltage | VTX-D+ + VTX-D- | / 2 Transition Time DC Differential TX Impedance 20% to 80% (1) 80 100 Conditions Min. 400 480 VDD0.3 150 120 ps Ohm Typ. Max. 600 720 Units CML Transmitter Output (100Ohm differential) VTX-DIFFP-P VTX-C tF, tR ZTX-DIFF-DC p-p
LVCMOS Control Pins VIH VIL IIH IIL VOH VOL Input High Voltage Input Low Voltage Input High Current Input Low Current DC Voltage Output High DC Voltage Output Low IOH = 4mA IOL = -4mA VDD 0.4 0.4 0.65 x VDD 0.35 x VDD 5 100 V
A V V
Note: 1. Using K28.7 (0011111000) pattern) 2. The parameter is determined by device characterization, and is not production tested
08-0329
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www..com
PI2EQX3201BL 3.0Gbps 2 Differential Channel Serial ReDriver Equalization, De-emphasis and Squelch
Packaging Mechanical: 36-pad TQFN (ZF36)
Notes: 1) All dimensions are in millimeters, angles in degrees 2) Bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. 3) Ref JEDEC: MO-220I/WJHD 4) Thermal Via Diameter. Recommended 0.2~0.33mm 5) Thermal Pitch. Recommended 1.27mm
DATE: 4/28/06
DESCRIPTION: 36-contact, Very Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZF36 DOCUMENT CONTROL #: PD-2023 REVISION: B
Ordering Information
Ordering Number PI2EQX3201BLZFE Package Code ZF Package Description Pb-Free and Green 36-pad TQFN
Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ * E = Pb-free and Green * X suffix = Tape/Reel
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
08-0329
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